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ID100 ID101
Linear Integrated Systems
FEATURES DIRECT REPLACEMENT FOR INTERSIL ID100 & ID101 REVERSE LEAKAGE CURRENT REVERSE BREAKDOWN VOLTAGE REVERSE CAPACITANCE ABSOLUTE MAXIMUM RATINGS @ 25 C (unless otherwise stated) Maximum Temperatures Storage Temperature Operating Junction Temperature Maximum Power Dissipation Continuous Power Dissipation Maximum Currents Forward Current Reverse Current Maximum Voltages Reverse Voltage Diode to Diode Voltage 30V 50V 20mA 100A 300mW -65 to +200 C -55 to +150 C
1
MONOLITHIC DUAL PICO AMPERE DIODES
IR = 0.1pA BVR 30V Crss = 0.75pF
ID100
ID101
TO-78 BOTTOM VIEW NC A1 K1
2 1 7 3 5 6
TO-71 BOTTOM VIEW NC A1 K1
2 1 7 3 5 6
NC A2 K2
NC A2 K2
ELECTRICAL CHARACTERISTICS @ 25 C (unless otherwise stated) SYMBOL BVR VF IR |IR1-IR2| Crss CHARACTERISTIC Reverse Breakdown Voltage Forward Voltage Reverse Leakage Current Differential Leakage Current Total Reverse Capacitance2 0.75 MIN 30 0.8 0.1 2.0 10 3 1 pF pA 1.1 TYP MAX UNITS V CONDITIONS IR = 1A IF = 10mA VR = 1V VR = 10V VR = 10V, f = 1MHz
Linear Integrated Systems
* 4042 Clipper Court * Fremont, CA 94538 * Tel: 510 490-9160 * Fax: 510 353-0261
Figure 1. Operational Amplifier Protection Input Differential Voltage limited to 0.8V (typ) by Diodes ID100 D1 and D2. Common Mode Input voltage limited by Diodes ID100 D3 and D4 to 15V. Figure 2. Sample and Hold Circuit Typical Sample and Hold circuit with clipping. ID100 diodes reduce offset voltages fed capacitively from the ID100 switch gate. FIGURE 1
ID100 D1 D3 D2 D4 OP-27 +
FIGURE 2
+V
ID100 D1
-V D2
+V
2N4117A
2N4393
C
ein
+15V -15V
CONTROL SIGNAL
R
VOUT
TO-78
0.305 0.335 0.335 0.370 MAX. 0.040 0.165 0.185 MIN. 0.500 SEATING PLANE 0.200 0.029 0.045
23 1 5 76
TO-71
Six Lead
0.195 DIA. 0.175 0.030 MAX. 0.230 DIA. 0.209 0.150 0.115
0.016 0.019 DIM. A 0.016 0.021 DIM. B
6 LEADS
0.019 DIA. 0.016 0.100
0.500 MIN.
0.100
0.050
23 1
0.100 45 0.028 0.034 45 0.046 0.036
7
5 6
0.048 0.028
1. 2. 3.
Absolute maximum ratings are limiting values above which serviceability may be impaired. Design reference only, not 100% tested. Pins 3 & 5 on ID100 and ID101 must not be connected, in any fashion or manner, to any circuit or node.
Information furnished by Linear Integrated Systems is believed to be accurate and reliable. However, no responsibility is assumed for its use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Linear Integrated Systems.
Linear Integrated Systems
* 4042 Clipper Court * Fremont, CA 94538 * Tel: 510 490-9160 * Fax: 510 353-0261

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